The present invention relates to semiconductor structures, and more particularly to a semiconductor structure which comprises at least one relaxed SiGe buffer layer formed on a silicon-on-insulator (SOI) substrate. The present invention is also directed to a method of fabricating at least one relaxed SiGe buffer layer having low threading dislocation (TD) densities on a SOI substrate.
The implementation of a strain-relaxed SiGe buffer layer (SiGeBL) in a heterostructure that contains at least one SiGe/Si interface, e.g., SiGe/Si(001) or SiGe/Si/SiO2/Si(001) (i.e., SiGe on SOI), offers a new degree of freedom in strain and band structure engineering. The tensile biaxial strain in a Si layer deposited on top of a SiGeBL leads to a conduction band offset at the interface that enables the formation of a two-dimensional-electron gas in a Si-quantum well (See, for example, K. Ismail, et al., Appl. Phys. Lett. 66, 1077 (1995) and U.S. Pat. No. 5,534,713 to K. Ismail, et al.). Extremely high electron mobility (about 5 times the value in bulk) has been measured at room temperature in tensile strained Si channels grown epitaxially on SiGeBLs (See, for example, K. Ismail ibid., or G. Hoeck, et al., Thin Solid Films 336, 1999 (2000)).
High frequency device characteristics demonstrate the outstanding potential of the SiGe/Si system. The state-of-the-art technique to produce high-quality SiGeBLs comprises the growth of several micrometer thick compositionally step-graded layers (with a typical Ge mole fraction of less than about 40%). Strain relaxation occurs by the formation of 60xc2x0 misfit dislocations at the SiGe/Si interface that terminate with threading dislocations (TDs) that thread through the SiGe layers at the wafer surface. Such strain-relaxed layers therefore have a TD density of about 104-107 cmxe2x88x922 (depending on the alloy composition) at the surface of the uppermost layer (See, for example, F. K. LeGoues, J. Appl. Phys. 71, 4230 (1992); U.S. Pat. No. 5,659,187 to F. K. LeGoues, et al.; E. A. Fitzgerald, et al., Appl. Phys. Lett. 59, 811 (1991); and G. Kissinger, et al., Appl. Phys. Lett. 66, 2083 (1995)).
The major drawbacks of prior art thick SiGeBLs (usually 1-5 micrometer thickness is necessary to obtain full strain relaxation with these relatively low TD densities) include: (1) the high TD density; and (2) the inhomogeneous distribution of TDs over the wafer surface, i.e., regions that have relatively low TD densities with primarily individual TDs and other areas that contain bundles of TDs that result from dislocation interactions such as blocking, multiplication, or dipole formation. As a result of dislocation blocking, surface pits that tend to line up in rows are found, thus making these regions of the wafer unusable for devices. (3) The thick graded SiGeBLs also result in self-heating effects in the devices because Ge has a lower thermal conductivity than Si. This makes devices fabricated on prior art SiGeBLs unsuitable for some applications.
Various prior art strategies have been developed to reduce the TD density. Such prior art strategies for reducing TD density include: (1) the use of an initial low-temperature buffer layer (See, for instance, T. Hackbath, et al. Thin Solid Films 339, 148 (2000); and (2) the use of hydrogen or helium implantation below the interface of a pseudomorphic SiGe layer on a Si substrate and subsequent annealing to create bubbles that give rise to heterogeneous dislocation nucleation. (See, H. Trinkaus, et al., Appl. Phys. Lett. 76, 3552 (2000) and D. M. Follstaedt, et al., Appl. Phys. Lett. 69, 2059 (1996)).
Prior art approaches (1) and (2) mentioned-above, are both based on the idea of creating extended defects that cause strain fields and thus enable the nucleation of dislocation loops. These loops extend to the SiGe/Si interface where they deposit a misfit dislocation segment and relieve strain. Since the half-loops terminate at these extended defects below the SiGe/Si interface, TDs are typically not formed (or are formed at much reduced densities).
A third prior art approach utilizes substrate patterning, e.g., etched trenches, to create comparatively small mesas on the order of about 10 to about 30 micrometers on a side. These trenches serve as a source (or a sink) for dislocations to nucleate/terminate. When a dislocation terminates at a trench, no TD is formed; however, the misfit segment present at the SiGe/Si interface contributes to strain relaxation; See, for instance, G. Woehl, et al. Thin Solid Films 369, 175 (2000).
Neither the conventional approaches to SiGeBLs, nor the alternative approaches to reduce the density of TDs described above provide a solution that fully satisfies the material demands for device applications, i.e., sufficiently low TD density and control over location of the TDs. In view of this, there is still a need for providing an alternative approach for fabricating strain-relaxed SiGeBLs on an SOI substrate that keeps the surface of the relaxed SiGeBL on which the actual device layers are subsequently deposited, essentially free of dislocations throughout all processing steps required to fabricate devices and circuits.
The present invention provides a method that keeps the topmost SiGe layer essentially free of dislocations, throughout all processing steps employed providing, nevertheless, at least one relaxed SiGeBL on an SOI substrate. This is achieved in the present invention by employing a method wherein a combined epitaxial growth and annealing procedure is employed.
Broadly speaking, the method of present invention comprises the steps of:
(a) forming a layer of self-assembled Ge or SiGe islands atop a Ge wetting layer which is formed on a top Si layer of a silicon-on-insulator (SOI) substrate;
(b) forming a planarizing Si or Si-rich SiGe cap layer which covers the layer of Ge or SiGe islands; and
(c) annealing the silicon-on-insulator substrate containing said planarizing Si or Si-rich SiGe cap layer covering said layer of Ge or SiGe islands so as to intermix said planarizing Si or Si-rich cap layer, said layer of Ge or SiGe islands and said top Si layer of the SOI substrate to relieve strain therein, thereby obtaining a homogeneous strain-relaxed SiGe layer directly on an oxide layer having a low density of threading dislocations.
The term xe2x80x9clow density of threading dislocationsxe2x80x9d is used herein to denote a structure wherein the TDs density is on the order of about 107 cmxe2x88x922 or less, with a density of from about 103 to about 106 cmxe2x88x922 being more highly preferred. The SiGe islands contain from about 30 atomic percent or greater Ge. The term xe2x80x9cSi-richxe2x80x9d cap layer denotes a cap layer that contains from about 90 atomic percent or greater Si.
In some embodiments of the present invention, a wetting layer consisting of a few monolayers of Ge are formed on the top Si layer prior to the formation of the layer of self-assembled Ge or SiGe islands. In another embodiment, an island nucleation layer comprised of less than one monolayer of C is formed on the top Si layer prior to formation of the wetting layer and/or the formation of the layer of self-assembled Ge or SiGe islands.
Another aspect of the present invention relates to a semiconductor structure which includes at least one strain-relaxed SiGe buffer layer formed utilizing the above processing steps on a surface of a SOI substrate.
Specifically, the inventive structure comprises:
a substrate having a top surface;
a first insulating layer atop of said substrate;
a first single crystalline relaxed SiGe layer atop said first insulating layer, wherein said first single crystalline relaxed SiGe layer has a uniform composition, is less than 200 nm thick, and has a threading dislocation density of less than about 107 cmxe2x88x922.
In some embodiments of the present invention, an optional intermediate layer which consists of a single crystalline relaxed SiGe layer of graded composition comprising between 0 atomic % Ge and the same atomic concentration of Ge present in the first single crystalline relaxed SiGe layer is formed atop the insulating layer. In such an embodiment, the first single crystalline relaxed SiGe layer is formed atop the optional intermediate layer.
In yet another embodiment of the present invention, a layer of homo-epitaxial SiGe layer is formed atop the first single crystalline relaxed SiGe layer. In yet another embodiment of the present invention, a layer of strained single crystalline SiGe or single crystalline Si containing zero atomic percent Ge is pseudomorphically formed atop the first single crystalline relaxed SiGe layer. In a further embodiment of the present invention, both the homo-epitaxial SiGe layer and the strained single crystalline pseudomorphically formed SiGe or Si layer are present atop the first single crystalline relaxed SiGe layer.
The present invention also contemplates integrated circuits (ICs) which include at least the semiconductor structure of the present invention and at least one semiconductor device. The present invention also contemplates forming a superlattice structure containing alternating SiGe layers atop the semiconductor structures of the present invention.